The present invention relates to level shifting, and in particular, to level shifter circuits and methods for maintaining duty cycle in level shift circuits.
Modern electronic systems comprise a wide variety of digital devices for processing, transmitting and/or storing digital data. Processing, transmitting and storing digital data often depends on the timing of a clock and/or other signals. The quality of the clock source limits the performance possible for a digital electronic system. For example, the reliability of the timing of electronic gates and clocks within the system affect the time a system must wait (e.g. set up and hold times) to latch the data at an input terminal or to perform other functions with that data. The more unreliable the transition timing of the clock signal, the longer the setup and hold times required by the system, and the poorer the system performance.
Often, different portions of an electronic system use different digital rail voltage values. For example, it is known in the art to have digital integrated circuits that use one set of rail voltage values internally (e.g., 0 and 1.8 volts for the digital zero and one values), and another set of rail voltage values to drive output pins (e.g. 0 and 5 volts for the digital zero and one values). Similarly, is known to have a system which uses lower voltage rails for one group of circuits, but uses higher voltage rails to drive a set of cables, or to use lower voltage rail values for reading data from memory cells, while using higher voltage rail values to drive circuitry external to those memory cells (see U.S. Pat. No. 4,903,327, issued to Rao). See also U.S. Pat. No. Re. 34,808, issued to Hsieh, which discusses circuitry for converting signals using TTL voltage levels to different voltage levels.
FIG. 1 illustrates a prior art CMOS level shifter circuit 100. Level shifter circuit 100 includes an inverter 101 coupled to a control terminal of a transistor 102. Level shifter circuit 100 utilizes a voltage range from ground to VD0 at an input terminal 104 and a voltage range from ground to VD1 at an output terminal 105. Voltage VD1 is greater than voltage VD0. Unfortunately, there is a mismatch between the timing characteristics of input signal CLKin and output signal CLKout. This is because when transistor 102 turns off, the rise time of signal CLKout is slowed by the output impedance of circuit 100 (depending primarily upon the effect of resistor R and the capacitance (not shown) on output terminal 105. In contrast, when signal CLKout falls, the output impedance is dominated by the on-resistance of transistor 102 (much lower than resistor R) and the above-mentioned capacitance. This mismatch of impedance skews transitions of output signal CLKout such that the duty cycle for output signal CLKout does not match the duty cycle of input signal CLKin.
FIG. 2 illustrates a prior art CMOS level shifter circuit 200. Level shifter circuit 200 includes transistors 201-204. Differential input signals CLKin+ and CLKin− drive the control input terminals of transistor 203 and 204, respectively. Transistors 201 and 202 are in a cross coupled configuration. When transistor 203 is switched on, the current passing through transistor 203 must overcome the current passing through transistor 201 in order to switch the level shifter output (CLKout−) to a low level. This delays and changes the timing of the rising and falling transitions of the output signals CLKout+ and CLKout− and skews the duty cycle.
The current passing through transistor 203 must overcome the current passing through the transistor 201 in order to switch the level shifter output (CLKout−) to a low level. A weaker drive for transistor 201 will improve the fall time of signal and degrade the rise time performance at the same time. Changes in supply voltage (Vdd2) may change the drive of transistor 201(/202) which may change the output rising(/falling) edges. Inconsistent rising (/falling) edges may degrade duty cycle performance.
Thus, there is a need for improved level shifting. A level shifter circuit in accordance with one embodiment of the present invention solves these and other problems by providing level shifter circuits and methods for maintaining duty cycle.